In recent years, the line width of circuit patterns formed in semiconductor devices has decreased with the miniaturization of memory device features. Memory devices have a multilayer wiring structure configured with a large number of wirings and wiring layers. The multilayer wiring is provided with a contact (via) that electrically connects an upper-layer wiring to a lower-layer wiring. By decreasing line widths, misalignment may occur between the upper-layer wirings and lower-layer wirings and a only partial overlap or complete lack of connection between the contact (via) and one or both of the upper lines and lower lines may occur as a result of the misalignment of the contact opening which is then filled with a conductor, with the upper and lower wiring layer locations.